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march 2010 doc id 17326 rev 1 1/56 56 L6717 high-efficiency hybrid am2r2 controller with i 2 c interface and embedded drivers features hybrid controller for both pvi and svi cpus dual controller with 2 embedded high current drivers + 2 pwm for external driver for cpu core and 1 embedded high current driver for cpu nb dynamic phase management (dpm) i 2 c interface to control offset, switching frequency and power management options dual-edge asynchronous architecture with ltb technology ? psi management to increase efficiency in light- load conditions dual overcurrent protection: total and per- phase accurate voltage positioning dual remote sense feedback disconnection protection programmable ov protection oscillator internally fixe d at 200 khz externally adjustable lsless startup to manage pre-biased output vfqfpn48 package applications hybrid high-current vrm / vrd for desktop / server / workstation / ipc cpus supporting pvi and svi interface high-density dc / dc converters description L6717 is a hybrid cpu power supply controller embedding 2 high-current drivers for the core section and 1 driver for the nb section - requiring up to 2 external drivers when the core section works at 4 phase to optimize the application over- all cost. i 2 c interface allows to manage offset both core and nb sections, switching frequency and dynamic phase management saving in component count, space and power consumption. dynamic phase management automatically adjusts phase-count according to cpu load optimizing the system efficiency under all load conditions. the dual-edge asynchronous architecture is optimized by ltb technology ? allowing fast load- transient response minimizing the output capacitor and reducing the total bom cost. fast protection against load over current is provided for both the sections. feedback disconnection protection prevents from damaging the load in case of disconnections in the system board. L6717 is available in vfqfpn48 package. vfqfpn48 vfqfpn48 table 1. device summary order codes package packing L6717 vfqfpn48 tr ay L6717 tr tape and reel www.st.com
contents L6717 2/56 doc id 17326 rev 1 contents 1 typical application cir cuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 8 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 hybrid cpu support and cpu_type detection . . . . . . . . . . . . . . . . . . 19 5.1 pvi - parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 pvi start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 svi - serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 svi start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.1 set vid command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.2 pwrok de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.3 psi_l and efficiency optimization at light-load . . . . . . . . . . . . . . . . . . . 24 5.4.4 hiz management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.5 hardware jumper override - v_fix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 power manager i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 power manager commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.1 overspeeding command (ovrspd) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.2 overvoltage threshold adjustment (ov_set) . . . . . . . . . . . . . . . . . . . . 30 6.1.3 switching frequency adjustment (fsw_adj) . . . . . . . . . . . . . . . . . . . . 30 6.1.4 droop function adjustment (drp_adj) . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.5 power management flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 dynamic phase management (dpm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
L6717 contents doc id 17326 rev 1 3/56 7 output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 core section - phase # programming . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 core section - current reading and current sharing loop . . . . . . . . . . . . 35 7.3 core section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4 core section - analog offset (optional - i2cdis = 3.3 v) . . . . . . . . . . . . 37 7.5 nb section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.6 nb section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.7 on-the-fly vid transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.8 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.8.1 ls-less start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 output voltage monitoring an d protections . . . . . . . . . . . . . . . . . . . . . 41 8.1 programmable overvoltage (i2dis = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.3 pwrgood . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4 overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4.1 core section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4.2 nb section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 high current embedded drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 boot capacitor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 system control loop compensati on . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12 ltb technology ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.1 power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2 small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 53 14 vfqfpn48 mechanical data and package dimensions . . . . . . . . . . . . 54 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
typical application circuit and block diagram L6717 4/56 doc id 17326 rev 1 1 typical application circuit and block diagram 1.1 application circuit figure 1. typical 4+1 application circuit h s 1 l s 1 l1 c hf c bulk_in s t L6717 (4+1) reference s chem a tic h s 2 l s 2 l2 c hf c out pwm 3 2 8 c s 1p 15 c s 1n 16 c s 2p 17 c s3 n 20 c s3 p 19 c mlcc c out_nb c mlcc_nb pvi / svid am2 cpu nb core l in 9 nb_fb nb_comp 10 fb 5 comp 4 o s c / en / flt 14 vid1 / core_type 33 vid 3 / s vc 3 1 vid4 / i2c_di s 3 0 vid5 / addre ss 29 pvi / s vid b us gnd_pad vcc 2 vid2 / s vd 3 2 st L6717 hybrid pvid / svid controller c f r f r fb c f_nb r f_nb r fb_nb r o s c r g r g r c r c r c boot pwm gnd lgate ugate vcc l674 3 b pha s e 3 4 1 3 5 vid0 / vfix pwrok pwrgood c lt b r lt b 8 lt b h s3 l s3 l 3 r c vcc boot pwm gnd lgate ugate l674 3 b pha s e h s 4 l s 4 l4 pwm4 27 c s 4n 22 c s 4p 21 r g r g 1 8 c hf c hf h s _nb l s _nb l_nb c hf 2 3 r_nb c_nb r g_nb 24 c s 2n nb_c s p nb_c s n ugate1 47 pha s e1 46 lgate1 45 ugate2 40 pha s e2 41 lgate2 44 nb_ugate 3 7 nb_pha s e 38 nb_lgate 4 3 6 v s en 7 fbg nb_v s en 11 nb_fbg 12 vccdrv 42 s da / ovp 25 s cl / o s 26 nb_boot 3 6 boot1 4 8 boot2 3 9 49 s gnd 3 . 3 v 3 . 3 v 3 svi/pvi interface c hf power m a n a ger i2c v in c hf ilim r ilim en en c i r i c p c ilim 5v s by q_en en 1 3
L6717 typical application circuit and block diagram doc id 17326 rev 1 5/56 figure 2. typical 3+1 application circuit h s 1 l s 1 l1 c hf c bulk_in s t L6717 ( 3 +1) reference s chem a tic h s 2 l s 2 l2 c hf c out pwm 3 2 8 c s 1p 15 c s 1n 16 c s 2p 17 c s3 n 20 c s3 p 19 c mlcc c out_nb c mlcc_nb pvi / svid am2 cpu nb core l in 9 nb_fb nb_comp 10 fb 5 comp 4 o s c / en / flt 14 vid1 / core_type 33 vid 3 / s vc 3 1 vid4 / i2c_di s 3 0 vid5 / addre ss 29 pvi / s vid b us gnd_pad vcc 2 vid2 / s vd 3 2 st L6717 hybrid pvid / svid controller c f r f r fb c f_nb r f_nb r fb_nb r g r g r c r c r c boot pwm gnd lgate ugate vcc l674 3 b pha s e 3 4 1 3 5 vid0 / vfix pwrok pwrgood c lt b r lt b 8 lt b h s3 l s3 l 3 pwm4 27 c s 4n 22 c s 4p 21 r g r g 1 8 c hf h s _nb l s _nb l_nb c hf 2 3 r_nb c_nb r g_nb 24 c s 2n nb_c s p nb_c s n ugate1 47 pha s e1 46 lgate1 45 ugate2 40 pha s e2 41 lgate2 44 nb_ugate 3 7 nb_pha s e 38 nb_lgate 4 3 6 v s en 7 fbg nb_v s en 11 nb_fbg 12 vccdrv 42 s da / ovp 25 s cl / o s 26 nb_boot 3 6 boot1 4 8 boot2 3 9 49 s gnd 3 . 3 v 3 svi/pvi interface c hf power m a n a ger i2c c hf v in ilim en c i r i c 14 r o s c r ilim c ilim 5v s by q_en en 1 3
typical application circuit and block diagram L6717 6/56 doc id 17326 rev 1 figure 3. typical 2+1 application circuit h s 1 l s 1 l1 c hf c bulk_in s t L6717 (2+1) re ference s chem a tic h s 2 l s 2 l2 c hf c out pwm 3 2 8 c s 1p 15 c s 1n 16 c s 2p 17 c s3 n 20 c s3 p 19 c mlcc c out_nb c mlcc_nb pvi / svid am2 cpu nb core l in 9 nb_fb nb_comp 10 fb 5 comp 4 o s c / en / flt 14 vid1 / core_type 33 vid 3 / s vc 3 1 vid4 / i2c_di s 3 0 vid5 / addre ss 29 pvi / s vid b us gnd_pad vcc 2 vid2 / s vd 3 2 st L6717 hybrid pvid / svid controller c f r f r fb c f_nb r f_nb r fb_nb r g r g r c r c 3 4 1 3 5 vid0 / vfix pwrok pwrgood c lt b r lt b 8 lt b pwm4 27 c s 4n 22 c s 4p 21 r g r g 1 8 h s _nb l s _nb l_nb c hf 2 3 r_nb c_nb r g_nb 24 c s 2n nb_c s p nb_c s n ugate1 47 pha s e1 46 lgate1 45 ugate2 40 pha s e2 41 lgate2 44 nb_ugate 3 7 nb_pha s e 38 nb_lgate 4 3 6 v s en 7 fbg nb_v s en 11 nb_fbg 12 vccdrv 42 s da / ovp 25 s cl / o s 26 nb_boot 3 6 boot1 4 8 boot2 3 9 49 s gnd 3 svi/pvi interface c hf power m a n a ger i2c c hf v in r g ilim c i r i c 14 r o s c r ilim c ilim 5v s by q_en en 1 3
L6717 typical application circuit and block diagram doc id 17326 rev 1 7/56 1.2 block diagram figure 4. block diagram nb_c s + dual channel o s cillator (4+1) L6717 control logic and i2c management current balance amd s vi / pvi flexible interface c s 2+ vid4 / i2cdi s vid5 / addr o s c / en pwrok pwrgood vcore_ref comp v s en fbg error amplifier fb vcc c s 1- s gnd c s 1+ i droop nb_pwm 64k 64k 64k 64k remote buffer nb_ref nb_comp nb_v s en nb_fbg error amplifier nb_fb 64k 64k 64k 64k remote buffer differential current s en s e output voltage monitor and protection management nb curr s en s e pwm2 pwm1 c s 2- c s3 + c s3 - c s 4+ c s 4- boot1 lgate1 pwm 3 pwm4 vcc s gnd i nb_droop (from s vi/pvi decoding) core_ref & nb_ref ilim c s 1- vid2 / s vd vid 3 / s vc vid0 / v_fix vid1 / core_type i lim s da / ovp s cl / o s boot1 ugate1 pha s e1 lgate1 boot2 ugate2 pha s e2 lgate2 ugate1 pha s e1 boot2 ugate2 pha s e2 lgate2 embedded driver core pha s e #1 embedded driver core pha s e #2 lt b ltb technology modulator nb_c s - nb_boot nb_ugate nb_pha s e nb_lgate embedded driver core nb pha s e nb_lgate nb_boot nb_ugate nb_pha s e vccdr gnd_pad vccdr vccdr
pins description and connection diagrams L6717 8/56 doc id 17326 rev 1 2 pins description and connection diagrams figure 5. pins connection (top view) 2.1 pin descriptions 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 3 6 3 5 3 4 33 3 2 3 1 3 0292 8 27 26 25 12 3 4567 8 9 101112 c s 1p c s 1n c s 2p c s 2n c s3 p c s3 n c s 4p c s 4n ilim nb_c s p nb_c s n o s c / en /flt boot1 ugate1 pha s e1 lgate1 lgate2 nb_lgate vccdrv pha s e2 ugate2 boot2 nb_pha s e nb_ugate nb_boot pwrgood vid0 / v_fix vid1 / coretype vid2 / s vd vid 3 / s vc vid4 / i2cdi s vid5 / addr pwm 3 pwm4 s cl / o s s da / ovp pwrok s gnd vcc comp fb v s en fbg lt b nb_comp nb_fb nb_v s en nb_fbg L6717 pad (gnd) table 2. pin description pin# name function 1pwrok system-wide power good input (ignored in pvi mode). internally pulled-low by 10 a. when low, the device will decode the two svi bits svc and svd to determine the pre-pwrok met a l vid . when high, the device will actively run the svi protocol. pre-pwrok met a l vid are latched after en is asserted and re-used in case of pwrok de-assertion. latch is reset by vcc or en cycle. 2sgnd device signal ground. all the internal references are referred to this pin. connect to the pcb signal ground. 3vcc device power supply. operative voltage is 12 15%. filter with 1 f mlcc to sgnd. do not connect vcc to an y voltage greater than vccdr. 4 core section comp core error ampl ifier output. connect with an r f - c f to fb. the core section and/or the device cannot be disabled by grounding this pin.
L6717 pins description and connection diagrams doc id 17326 rev 1 9/56 5 core section fb core error amplifier inverting input. connect with a resistor r fb to vsen and with an r f - c f to comp. droop current for voltage positioning is sourced from this pin. 6vsen core output voltage monitor. it manages ovp and uvp protections and pwrgood. connect to the positive side of the load for remote sensing. see s ection 8 for details. 7fbg core remote ground sense. connect to the negative side of the load for remote sensing. see s ection 11 for proper layout of this connection. 8ltb ltb technology ? input pin. connect through an r lt b - c lt b network to the regulated voltage (core section) to detect load transient. see s ection 12 for details. 9 nb section nb_comp nb error amplifier output. connect with an r f_nb - c f_nb to nb_fb. the nb section and/or the device cannot be disabled by grounding this pin. 10 nb_fb nb error amplifier inverting input. connect with a resistor r fb_nb to nb_vsen and with an r f_nb - c f_nb to nb_comp. droop current for voltage positioning is sourced from this pin. 11 nb_vsen nb output voltage monitor. it manages ovp and uvp protections and pwrgood. connect to the positive side of the nb load to perform remote sensing. see s ection 11 for proper layout of this connection. 12 nb_fbg nb remote ground sense. connect to the negative side of the load to perform remote sense. see s ection 11 for proper layout of this connection. 13 core section ilim core over current pin. a current i lim =dcr/r g *i out proportional to the current delivered by the core section is sourced from this pin. the oc threshold is programmed by connecting a resistor r ilim to sgnd. when the generated voltage crosses the oc_tot threshold (v oc_tot = 2.5v typ) the device latches with all mosfets off (to recover, cycle vcc or the en pin). this pin is monitored for dynamic phase management. filter with proper capacitor to provide oc masking time; do not exceed 30 sec. see s ection 8.4.1 for details. 14 osc / en / flt o s c : it allows programming the switching frequency f sw of both sections. switching frequency can be increased according to the resistor r osc connected to sgnd with a gain of 9.1khz/a (see s ection 9 for details). if floating, the switching frequency is 200khz per phase. en : pull-low (tie to gnd) to disable the device. when set free, the device immediately checks for the vid1 status to determine the svi / pvi protocol to be adopted and configures itself accordingly. flt : the pin is internally forced high (3.3v) in case of an ov / uv fault. to recover from this condition, cycle vcc or the en pin. to enable/disable the ic drive osc/en/faut pin by an open drain circuit. table 2. pin description (continued) pin# name function
pins description and connection diagrams L6717 10/56 doc id 17326 rev 1 15 core section cs1p channel 1 current sense positive input. connect through an r-c filter to the pha se-side of the channel 1 inductor. see s ection 11 for proper layout of this connection. 16 cs1n channel 1 current sense negative input. connect through a r g resistor to the output-side of the channel inductor. filter the vout-side of r g resistor with 100nf to gnd. see s ection 11 for proper layout of this connection. 17 cs2p channel 2 current sense positive input. connect through an r-c filter to the pha se-side of the channel 2 inductor. see s ection 11 for proper layout of this connection. 18 cs2n channel 2 current sense negative input. connect through a r g resistor to the output-side of the channel inductor. filter the vout-side of r g resistor with 100nf to gnd. see s ection 11 for proper layout of this connection. 19 cs3p channel 3 current sense positive input. connect through an r-c filter to the phase -side of the channel 3 inductor. when working at 2 phase, directly connect to v out_core . see s ection 11 for proper layout of this connection. 20 cs3n channel 3 current sense negative input. connect through a r g resistor to the output-side of the channel inductor. when working at 2 phase, connect through r g to cs3+. filter the vout-side of r g resistor with 100nf to gnd. see s ection 11 for proper layout of this connection. 21 cs4p channel 4 current sense positive input. connect through an r-c filter to the phase -side of the channel 4 inductor. when working at 2 or 3 phase, directly connect to v out_core . see s ection 11 for proper layout of this connection. 22 cs4n channel 4 current sense negative input. connect through a r g resistor to the output-side of the channel inductor. when working at 2 or 3 phase, connect through r g to cs4+.filter the vout-side of r g resistor with 100nf to gnd. see s ection 11 for proper layout of this connection. 23 nb section nb_csp nb channel current sense positive input. connect through an r-c filter to the phase -side of the nb channel inductor. see s ection 11 for proper layout of this connection. 24 nb_csn nb channel current sense negative input. connect through a r g resistor to the output-side of the channel inductor. filter the vout-side of r g resistor with 100nf to gnd. see s ection 11 for proper layout of this connection. table 2. pin description (continued) pin# name function
L6717 pins description and connection diagrams doc id 17326 rev 1 11/56 25 power manager i 2 c sda / ovp s da - power m a n a ger i 2 c d a t a . when power manager i 2 c is enabled, this is the data connection. see s ection 6 for details. ovp - over volt a ge setting . when power manager i 2 c is disabled (vid4 / i2cdis to 3.3v) the pin is used to set the ovp protection for core and nb sections. define the ovp threshold by connecting the pin to the center tap of a voltage divider from 3v3 to sgnd. see s ection 8.1 for details. 26 scl / os s cl - power m a n a ger i 2 c clock . when power manager i 2 c is enabled, this is the clock connection. see s ection 6 for details. o s - core section offset . when power manager i 2 c is disabled (vid4 / i2cdis to 3.3v) this pin is internally set to 1.24v(2.0v): connecting a r os resistor to gnd (3.3v) allows setting a current that is mirrored into fb pin in order to program a positive (negative) offset according to the selected r fb . short to gnd to disable the function. see s ection 7.4 for details. 27, 28 pwm4, pwm3 pwm output for external drivers. connect to external drivers pwm inputs. the device is able to manage hiz status by setting the pins floating. by shorting to gnd pwm4 or pwm3 and pw m4, it is possible to program the core section to work at 3 or 2 phase respectively. see s ection 5.4.4 for details about hiz management. 29 svi / pvi interface vid5 / addr voltage identification pin - i 2 c address pin. internally pulled-low by 10 a, it programs the output vo ltage in pvi mode. in svi mode, the pin is monitored on the en pin rising-edge to modify the i 2 c address. see s ection 5 for details. 30 vid4 / i2cdis voltage identification pin - i 2 c disable pin. internally pulled-low by 10 a, it programs the output vo ltage in pvi mode. in svi mode, the pin is monitored on the en pin rising-edge to enable/disable the i 2 c . see s ection 5 for details. 31 vid3 / svc voltage identification pin - svi clock pin. internally pulled-low by 10 a, it programs the output vo ltage in both svi and pvi modes. in svi mode, the 10 a pull down is disabled. see s ection 5 for details. 32 vid2 / svd voltage identification pins - svi data pin. internally pulled-low by 10 a, it programs the output vo ltage in both svi and pvi modes. in svi mode, the 10 a pull down is disabled. see s ection 5 for details. 33 svi / pvi interface vid1 / coretype voltage identification pin. internally pulled-low by 10 a, it programs the output volt age in pvi mode. the pin is monitored on the en pin rising-edge to def ine the operative mode of the controller (svi or pvi). see s ection 5 for details. 34 vid0 / vfix voltage identification pin. internally pulled-low by 10 a, it programs the output voltage in pvi mode. if the pin is pulled to 3.3v, the device enters v_fix mode and svi commands are ignored. see s ection 5 for details. table 2. pin description (continued) pin# name function
pins description and connection diagrams L6717 12/56 doc id 17326 rev 1 35 pwrgood vcore and nb power good. it is an open-drain output set free after ss as long as both the voltage planes are within specifications. pull-up to 3.3v (typ) or lower, if not used it can be left floating. when in pvi mode, it monitors the core section only. 36 embedded drivers nb_boot nb section high-side driver supply. this pin supplies the high-side floating driver. connect through c boot capacitor to the nb_phase pin. see s ection 10 for guidance in designing the capacitor value. 37 nb_ugate nb section high-side driver output. connect to nb section high-side mosfet gate. a small series resistor may help in reducing nb_phase pin negative spike as well as cooling the device. 38 nb_phase nb section high-side driver return path. connect to the nb section high-side mosfet source. this pin is also monitored for the adaptive dead-time management. 39 boot2 core section, phase 2 high-side driver supply. this pin supplies the high-side floating driver. connect through c boot capacitor to the phase2 pin. see s ection 10 for guidance in designing the capacitor value. 40 ugate2 high-side driver output. connect to phase2 high-side mosfet gate. a small series resistor may help in reducing phase2 pin negative spike as well as cooling the device. 41 phase2 core section, phase 2 high-side driver return path. connect to the phase2 high-side mosfet source. this pin is also monitored for the adaptive dead-time management. 42 vccdrv supply voltage for low-side embedded drivers. operative voltage is flexible from 5v 5% to 12 15%. filter with 1 f mlcc to gnd. do not connect vcc to an y voltage greater than vccdr. 43 to 45 embedded drivers nb_lgate, lgate2, lgate1 low-side driver output. connect directly to the low-side mosfet gate of the related section. a small series resistor can be useful to reduce dissipated power especially in high frequency applications. 46 phase1 core section, phase 1 high-side driver return path. connect to the phase1 high-side mosfet source. this pin is also monitored for the adaptive dead-time management. 47 ugate1 high-side driver output. connect to phase1 high-side mosfet gate. a small series resistor may help in reducing phase1 pin negative spike as well as cooling the device. 48 boot1 core section, phase 1 high-side driver supply. this pin supplies the high-side floating driver. connect through c boot capacitor to the phase1 pin. see s ection 10 for guidance in designing the capacitor value. thermal pa d gnd all internal references, logic, and the silic on substrate are referenced to this pin. connect to the pcb gnd ground plane by mult iple vias to improve heat dissipation. table 2. pin description (continued) pin# name function
L6717 pins description and connection diagrams doc id 17326 rev 1 13/56 2.2 thermal data table 3. thermal data symbol parameter value unit r thja thermal resistance junction to ambient (device soldered on 2s2p pc board) 40 c/w r thjc thermal resistance junction to case 1 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range 0 to 125 c
electrical specifications L6717 14/56 doc id 17326 rev 1 3 electrical specifications 3.1 absolute maximum ratings table 4. absolute maximum ratings symbol parameter value unit v cc, v ccdrv to gnd -0.3 to 15 v v bootx , v ugatex to gnd to phasex 41 15 v v phasex to gnd to gnd, t < 200nsec. -8 to 26 30 v v lgatex to gnd to gnd, t < 100nsec. -0.3 to vccdrv + 0.3 -3 v all other pins to gnd -0.3 to 3.6 v maximum withstanding voltage range test condition: cdf-aec-q100-002- ?human body model? acceptance ?normal performance? 1750 v
L6717 electrical specifications doc id 17326 rev 1 15/56 3.2 electrical characteristics v cc =12 v15%, t j = 0 c to 70 c unless otherwise specified. table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit supply current and power-on i cc vcc supply current osc = gnd 15 ma i ccdr vccdr supply current 4 ma i bootx bootx supply current 1.5 ma uvlo vcc vcc turn-on vcc rising 4.5 v vcc turn-off vcc falling 4 v oscillator f sw main oscillator accuracy 180 200 220 khz oscillator adjustability r osc = 36k 425 500 575 khz v osc pwm ramp amplitude core and nb section 1.5 v fault voltage at pin osc ovp, uvp latch active 3 3.6 v en turn-off threshold osc/en falling 0.3 v pvi / svi interface pwrok input high 1.3 v input low 0.80 v vid2,/svd vid3/svc input high (svi mode) 0.95 v input low (svi mode) 0.65 v svd voltage low (ack) i sink = -5ma 250 mv vid0 to vid5 input high (pvi mode) 1.3 v input low (pvi mode) 0.80 v v_fix entering v_fix mode vid0/v_fix rising 3 v power manager i 2 c sda, scl input high 1.3 v input low 0.8 v sda voltage low (ack) i sink = -5ma 250 mv
electrical specifications L6717 16/56 doc id 17326 rev 1 voltage positioning (core and nb section) core output voltage accuracy vsen to v core ; fbg to gnd core -8 8 mv nb nbvsen to v nb ; nbfbg to gnd fb -10 10 mv os offset bias voltage i2dis=3.3v, i os = 0 to 250 a 1.190 1.24 1.290 v offset current range i2dis=3.3v 0 250 a offset - i fb accuracy i2dis=3.3v, i os = 0 a -2.25 2.25 a i2dis=3.3v, i os = 250 a-9 9 a droop droop accuracy i droop = 0 to 25 a, k drp = 1/4 -3 3 a i nb_droop = 0 to 6 a, k nbdrp = 1/4 -1 1 a a 0 ea dc gain 100 db sr slew rate comp, nb_comp to sgnd = 10pf 20 v/ s pwm outputs (core only) and embedded drivers pwm3, pwm4 output high i = 1ma 3 3.6 v output low i = -1ma 0.2 v i pwmx test current 10 a high current embedded drivers r hihs hs source resistance boot - phase = 12v; 100ma 2.3 2.8 i ugate hs source current boot - phase = 12v; (1) c ugate to phase = 3.3nf 2a r lohs hs sink resistance boot - phase = 12v; 100ma 2 2.5 r hils ls source resistance 100ma 1.3 1.8 i lgate ls source current c lgate to gnd = 5.6nf, (1) 3a r lols ls sink resistance 100ma 1 1.5 protections ovp over voltage protection i 2 c enabled, no commands issued, wrt vid, core & nb section +200 +250 +300 mv i 2 c disabled, v_fix mode; vsen, nb_vsen rising 1.800 v sda/ovp bias current i2cdis = 3.3v 9 11 13 a uvp under voltage protection vsen, nb_ vsen falling; wrt ref. -450 -400 -350 mv pwrgood pgood threshold vsen, nb_vsen fa lling; wrt ref -285 -250 -215 mv voltage low i pwrgood = -4ma 0.4 v v fb-disc fb disconnection v csn rising, above vsen core and nb sections 600 mv v fbg disc fbg disconnection ea ni input wrt vid 500 mv table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
L6717 electrical specifications doc id 17326 rev 1 17/56 v oc_tot core oc 2.425 2.500 2.575 v ki ilim i lim = 0 a04 a i lim = 100 a100 a 1. parameter(s) guaranteed by desi gned, not fully tested in production table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
device description and operation L6717 18/56 doc id 17326 rev 1 4 device description and operation L6717 is a hybrid cpu power supply controller compatible with both par allel (pvi) and serial (svi) protocols for amd processors. the device provides complete control logic and protections for a high-performance step-down dc-dc voltage regulator, optimized for advanced microprocessor power supply supporting both pvi and svi communication. it embeds two independent controllers for cpu core and the integrated nb, each one with its own set of protections. nb phase (when enabled) is automatically phase-shifted with respect to the core phases in order to reduce the total input rms current amount. the device features an additional power manager i 2 c interface to ea sy the system design for enthusiastic application where the main parameters of the voltage regulator have to be modified. L6717 is able to adjust the regulated voltage, the switching frequency and also the ov protection threshold through the power manager i 2 c bus while the app lication is running assuring fast and reliable transitions. dynamic phase management (dpm) allows the de vice to automatically adjust the phase count according to the current delivered to the load. this feature allow the system to keep alive only the phases really necessary to sustain the load saving in power dissipation so optimizing the efficiency over the whole current range of the application. dpm can be enabled through the power manager i 2 c bus. L6717 is able to detect which kind of cpu is conn ected in order to configure itself to work as a single-plane pvi controller or dual-plane svi controller. the controller performs a single-phase control for the nb section and a programmable 2-to- 4 phase control for the core section featuring dual-edge non-latched architecture: this allows fast load-transient response optimizing the output filter consequently reducing the total bom cost. further reduction in output filter can be achieved by enabling ltb technology ? . psi_l flag is sent to the vr through the svi bus. the controller monitors this flag and selectively modifies the phase number in order to optimize the system efficiency when the cpu enters low-power states. this causes the over-all efficiency to be maximized at light loads so reducing losses and system power consumption. both sections feature programmable overvoltage protection and adjustable constant overcurrent protection. voltage positioning (ll) is possible thanks to an accurate fully- differential current-sense across the main inductors for both sections. L6717 features dual remote sensing for the regulated outputs (core and nb) in order to recover from pcb voltage drops also protecting the load from possible feedback network disconnections. lsless start-up function allows the controller to manage pre-biased start-up avoiding dangerous current return through the main inductors as well as negative undershoot on the output voltage if the output filter is still charged before start-up. L6717 supports v_fix mode for system debugging: in this particular configuration the svi bus is used as a static bus configuring 4 operative voltages for both the sections and ignoring any serial-vid command. when working in pvi mode, the device features on-the-fly vid management: vid code is continuously sampled and the reference update according to the variation detected, L6717 is available in vfqfpn48 package.
L6717 hybrid cpu support and cpu_type detection doc id 17326 rev 1 19/56 5 hybrid cpu support and cpu_type detection L6717 is able to detect the type of the cpu-core connected and to configure itself accordingly. at system start-up, on the rising-edge of the en signal, the device monitors the status of vid1 and configures the pvi mode (vid1 = 1) or svi mode (vid1 = 0). when in pvi mode, L6717 uses the information available on the vid[0: 5] bus to address the core section output voltage according to t a ble 6 . nb section is kept in hiz mode, both mosfets are kept off. when in svi mode, L6717 ignores the information available on vid0, vid4 and vid5 and uses vid2 and vid3 as a svi bus addressing the core and nb sections according to the svi protocol. caution: to avoid any risk of errors in cpu type detection (i.e. detecting svi cpu when pvi cpu is installed on the socket and vice versa), it is recommended to carefully control the start-up sequencing of the system hosting L6717 in order to ensure than on the en rising-edge, vid1 is in valid and correct state. typical connections consider vid1 connected to cpu core_type through a resistor to correctly address the cpu detection. 5.1 pvi - parallel interface pvi is a 6-bit-wide parallel inte rface used to address the core section reference. according to the selected code, the device sets the co re section reference and regulates its output voltage as reported into t a ble 6 . nb section is always kept in hiz; no activity is performed on this section and both the high- side and low-side of this section are kept of f. furthermore, pwrok information is ignored as well since the signal only applies to the svi protocol. 5.2 pvi start-up once the pvi mode has been detected, the device uses the whole code available on the vid[0:5] lines to define the reference for the core section. nb section is kept in hiz. soft- start to the programmed reference is performed regardless of the state of pwrok. see s ection 7.8 for details about soft-start.
hybrid cpu support and cpu_type detection L6717 20/56 doc id 17326 rev 1 table 6. voltage identifications (vid) codes for pvi mode vid5 vid4 vid3 vid2 vid1 vid0 output voltage vid5 vid4 vid3 vid2 vid1 vid0 output voltage 0000001.55001000000.7625 0000011.52501000010.7500 0000101.50001000100.7375 0000111.47501000110.7250 0001001.45001001000.7125 0001011.42501001010.7000 0001101.40001001100.6875 0001111.37501001110.6750 0010001.35001010000.6625 0010011.32501010010.6500 0010101.30001010100.6375 0010111.27501010110.6250 0011001.25001011000.6125 0011011.22501011010.6000 0011101.20001011100.5875 0011111.17501011110.5750 0100001.15001100000.5625 0100011.12501100010.5500 0100101.10001100100.5375 0100111.07501100110.5250 0101001.05001101000.5125 0101011.02501101010.5000 0101101.00001101100.4875 0101110.97501101110.4750 0110000.95001110000.4625 0110010.92501110010.4500 0110100.90001110100.4375 0110110.87501110110.4250 0111000.85001111000.4125 0111010.82501111010.4000 0111100.80001111100.3875 0111110.77501111110.3750
L6717 hybrid cpu support and cpu_type detection doc id 17326 rev 1 21/56 5.3 svi - serial interface svi is a two wire, clock and data, bus that connects a single master (cpu) to one slave (L6717). the master initiates and terminates svi transactions and drives the clock, svc, and the data, svd, during a transaction. the slave receives the svi transactions and acts accordingly. svi wire protocol is based on fast-mode i 2 c. svi interface also considers two additional signal needed to manage the system start-up. these signals are en and pwrok. the device return a pwrgood signal if the output voltages are in regulation. 5.4 svi start-up once the svi mode has been detected on the en rising-edge, L6717 checks for the status of the two serial vid pins, svc and svd, and stores this value as the pre-pwrok met a l vid . the controller initiate a soft-start phase regulating both core and nb voltage planes to the voltage level prescribed by the pre-pwrok met a l vid . see t a ble 7 for details about pre-pwrok met a l vid codifications. the stored pre-pwrok met a l vid value are re-used in any case of pwrok de-assertion. after bringing the output rails into regulation, the controller asserts the pwrgood signal and waits for pwrok to be asserted. until pwrok is asserted, the controller regulates to the pre-pwrok met a l vid ignoring any commands coming from the svi interface. after pwrok is asserted, the processor has initialized the serial vid interface and L6717 waits for commands from the cpu to move the voltage planes from the pre-pwrok met a l vid values to the operative vid values. as long as pwrok remains asserted, the controller will react to any command issu ed through the svi in terface according to svi protocol. see s ection 7.8 for details about soft-start. table 7. v_fix mode and pre-pwrok metalvid 5.4.1 set vid command the set vid comm a nd is defined as the command sequence that the cpu issues on the svi bus to modify the voltage level of the core section and/or the nb section. during a set vid comm a nd , the processor sends the start (start) sequence followed by the address of the section which the set vid comm a nd applies. the processor then sends the write (write) bit. after the write bit, the voltage regulator (vr) sends the acknowledge (ack) bit. the processor then sends the vid bits code during the d a t a ph a se . the vr sends the acknowledge (ack) bit after the data phase. finally, the processor sends the stop (stop) sequence. after the vr has detected the stop, it performs an on-the-fly vid svc svd output voltage [v] pre-pwrok metal vid v_fix mode 0 0 1.1v 1.4v 0 1 1.0v 1.2v 1 0 0.9v 1.0v 1 1 0.8v 0.8v
hybrid cpu support and cpu_type detection L6717 22/56 doc id 17326 rev 1 transition for the addressed section(s) or, more in general, react to the sent command accordingly. refer to figure 6 , t a ble 8 and t a ble 9 for details about the set vid comm a nd. L6717 is able to manage individual power off for both the sections. the cpu may issue a serial vid command to power off or power on one section while the other one remains powered. in this case, the pwrgood signal remains asserted. figure 6. svi communications - send byte table 8. svi send byte - address and data phase description bits description address phase 6:4 always 110b. 3 not applicable, ignored. 2 not applicable, ignored. 1 core section (1) . if set then the following data byte contains the vid code for core section. 1. assertion in both bit 1 and 0 will address t he vid code to both core and nb simultaneously. 0 nb section (1) . if set then the following data byte contains the vid code for nb section. data phase 7 psi_l flag (active low).when asserted, t he vr is allowed to enter power-saving mode. see s ection 5.4.3 . 6:0 vid code. see t a ble 9 . s vc s vd s tart 110 b ack ack slave addre ss ing (7 clock s ) 654 0 write (1ck) ack (1ck) 760 3 data pha s e ( 8 clock s ) ack (1ck) s top s tart s lave addre ss ing + w ack data pha s e ack s top bu s driven by L6717 bu s driven by ma s ter (cpu)
L6717 hybrid cpu support and cpu_type detection doc id 17326 rev 1 23/56 table 9. data phase - serial vid codes svi [6:0] output voltage svi [6:0] output voltage svi [6:0] output voltage svi [6:0] output voltage 000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.3500 000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.3375 000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.3250 000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.3125 000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110_0100 0.3000 000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110_0101 0.2875 000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110_0110 0.2750 000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110_0111 0.2625 000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110_1000 0.2500 000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110_1001 0.2375 000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110_1010 0.2250 000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110_1011 0.2125 000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110_1100 0.2000 000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110_1101 0.1875 000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110_1110 0.1750 000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110_1111 0.1625 001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111_0000 0.1500 001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111_0001 0.1375 001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111_0010 0.1250 001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111_0011 0.1125 001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111_0100 0.1000 001_0101 1.2875 011_0101 0.8875 101_0101 0.4875 111_0101 0.0875 001_0110 1.2750 011_0110 0.8750 101_0110 0.4750 111_0110 0.0750 001_0111 1.2625 011_0111 0.8625 101_0111 0.4625 111_0111 0.0625 001_1000 1.2500 011_1000 0.8500 101_1000 0.4500 111_1000 0.0500 001_1001 1.2375 011_1001 0.8375 101_1001 0.4375 111_1001 0.0375 001_1010 1.2250 011_1010 0.8250 101_1010 0.4250 111_1010 0.0250 001_1011 1.2125 011_1011 0.8125 101_1011 0.4125 111_1011 0.0125 001_1100 1.2000 011_1100 0.8000 101_1100 0.4000 111_1100 off 001_1101 1.1875 011_1101 0.7875 101_1101 0.3875 111_1101 off 001_1110 1.1750 011_1110 0.7750 101_1110 0.3750 111_1110 off 001_1111 1.1625 011_1111 0.7625 101_1111 0.3625 111_1111 off
hybrid cpu support and cpu_type detection L6717 24/56 doc id 17326 rev 1 5.4.2 pwrok de-assertion anytime pwrok de-asserts, while en is asserted, the controller uses the previously stored pre-pwrok met a l vid and sets both core and nb planes voltage to the corresponding level performing an on-the-fly vid transition. anytime the pwrok is de-asserted the pwrgood is tied low; after being pulled low the pwrgood is treated appropriately and kept de-asserted until the output voltage of both core and nb sections is within the pwrgood validity window referred to pre-pwrok met a l vid. 5.4.3 psi_l and efficiency optimization at light-load psi_l is an active-low flag (i.e. low logic level when asserted) that can be set by the cpu to allow the vr to enter power-saving mode to maximize the system efficiency when in light- load conditions. the status of the flag is communicated to the controller through the svi bus. when the psi_l flag is asserted by the cpu through the svi bus, the device adjusts the phase number according to the programmed strategy. default psi_l strategy consists in working in single phase. psi_l strategy can be disabled as well as re-configured through specific power manager i 2 c commands. see s ection 6 for details. when cpu issues psi_l flag, L6717 adjusts phase number according to the selected psi_l strategy: the device sets hiz on the related phases and re-configures internal phase- shift to maintain the correct interleaving among active phases. furthermore, the internal current-sharing is adjusted considering the phase number reduction. when psi_l is de-asserted, the device will return to the original configuration. start-up is performed with all the configured phases enabled. when psi_l is active L6717 performs on-the-fly vid transitions with all the programmed phases. nb section is not impacted by psi_l status change. figure 7 shows an example of the efficiency improvement that can be achieved by enabling the psi management. figure 7. system efficiency enhancement by psi 1 phase 4 phase 1 phase 4 phase
L6717 hybrid cpu support and cpu_type detection doc id 17326 rev 1 25/56 5.4.4 hiz management L6717 is able to manage hiz both for internal driver and for external drivers through the pwmx signals. when the controller needs to set hiz state for a phase or section, it sets the corresponding pwmx pin floating and, at the same time, turn off both hs and ls mosfets by proper action of the corresponding embedded driver. 5.4.5 hardware jumper override - v_fix vid0/v_fix pin allows the device to operate in v_fix mode. anytime L6717 is enabled it checks the pin vid0/v_fix voltage level: pull up vid0/v_fix to 3.3v to enter v_fix mode. when in v_fix mode, both nb and core section voltages are governed by the information shown in t a ble 7 . regardless of the state of vid1, the device will work in svi mode and furthermore pwrok logic level is ignored. svc and svd are considered as static vid and the output voltage changes according to their status. dynamic svc/svd-change management is provided in this condition. v_fix mode is intended for system debug only. protection management differs in this case, see s ection 8.1 for details.
power manager i2c L6717 26/56 doc id 17326 rev 1 6 power manager i 2 c L6717 features a secondary power manager i 2 c bus to easy the implementation of power management features as well as over-speeding for ?enthusiastic? users. the power manager i 2 c bus is operative after the pwrgood signal is driven high at the end of the soft-start. power manager i 2 c is a two wire, scl (clock) and sda (data), bus connecting a single master to one or more slaves (L6717) separately addressable. the master initiates and terminates i 2 c transactions and drives both the clock, scl, and the data, sda, during a transaction. the slave receives the i 2 c transactions and acts accordingly. power manager i 2 c wire protocol is based on fast-mode i 2 c. power manager i 2 c address configuration can be programmed through addr pin while i2cdis pin allows to disable the bus. see t a ble 10 . power manager i 2 c and svi bus are two independent buses working in parallel. in case two commends are issued in the same time on the two buses, L6717 performs them in the same time. table 10. power manager i 2 c configuration 6.1 power manager commands power manager i 2 c master issues different command sequences to modify several voltage positioning parameters for core and/or nb sections of L6717. moreover the power manager i 2 c commands allow to configure dpm and other power- saving-related features. during a power m a n a ger comm a nd : ? the bus master sends the start (start) sequence followed by the a ddress of the controller which the power m a n a ger comm a nd applies. the bus master then sends the write (write) bit. after the write bit, the voltage regulator (vr, L6717) sends the acknowledge (ack) bit. ? the bus master sends the command code during the comm a nd ph a se . the vr (L6717) sends the acknowledge (ack) bit after the command phase. ? the bus master sends the d a t a stre a m related to the command phase previously issued (if applicable). the vr (L6717) s ends the acknowledge (ack) bit after the data stream. finally, the bus master sends the stop (stop) sequence. ? after the vr (L6717) has detected the stop sequence, it performs operations according to the command is sued by the bus master. i2cdis addr description 3.3v n/a power manager i 2 c disabled. sda/ovp now becomes ovp to program the ov threshold for both core and nb sections. scl/os now becomes os to program offset for the core section. open 3.3v it sets i 2 c address to 1100111. open it sets i 2 c address to 1100110 (default).
L6717 power manager i2c doc id 17326 rev 1 27/56 refer to figure 8 , t a ble 11 and t a ble 12 for details . figure 8. power manager i 2 c communication format table 11. power manager i 2 c - address and command phase description bits description address phase 1:6 always 110011b. 7 slave address. according to addr connection, the device will act if addressed by 0b or 1b. default address bit is 0b. 8write bit. command phase 1:3 not applicable, ignored. 4:6 command code 7, 8 not applicable, ignored. command
power manager i2c L6717 28/56 doc id 17326 rev 1 table 12. power manager i 2 c command phase and data stream command code [4:6] data stream [1:8] description 1cn [1:2] xx [3] sign [4:8] ovrspd over s peeding : adds a positive/negative offset to the regulation according to the sign bit with 50mv lsb and 5bit resolution. [3] sign: 1b for positive offset, 0b for negative offset. negative offset is applicable only to core section (nb does not react to negative os command) [4:8] ovrspd: 5bit code (4:msb to 8:lsb), defines the offset to add to the programmed reference (vid). maximum core output voltage re achable is limited to 2.8v. maximum nb output voltage reachable is limited by the maximum nb offset: +600mv (over vid) ?cn? bits in comm a nd code address core section (?c? bit) or nb section (?n? bit) if set to 1b. asserting both c and n bits will apply the command to both core and nb section. see t a ble 13 for details about ovrspd codification. 000 [1:4] xxxx [5:6] ov_nb [7:8] ov_core ov_ s et : overvoltage threshold setup fo r core and/or nb sections. sets the ov threshold above the programmed vid (including ovrspd) in with three 200mv steps from + 250mv up to +850mv (up to 650mv for nb). [1:4]: ignored [5:6] ov_nb: northbridge ovp . 2bit code, defines the ov threshold for the nb section above the programmed reference (vid). [7:8] ov_core: core ovp . 2bit code, defines the ov threshold for the core section above the programmed reference (vid). default ov threshold is +250mv above reference for both sections. see t a ble 14 for details about ov_set codification. 001 [1:5] xxxxx [6:8] fsw f s w_adj: switching frequency adjustment. modifies the switching frequency programmed through osc pin according to fsw code by +/- 10% or +/-20%. [1:5]: ignored [6:8]: fsw: s witching frequency a djustment . 3 bits code to adjust the switching frequency with respect programmed voltage. see t a ble 15 for details about fsw_adj codification.
L6717 power manager i2c doc id 17326 rev 1 29/56 6.1.1 overspeeding command (ovrspd) this command allows to add a variable positive/negative offset to the core and/or nb reference programmed by the svi bus in order to overspeed the cpu. L6717 allows adding up to 1.550 v in 50 mv steps to the reference. the maximum possible output voltage for core sect ion is internally limited to 2.8 v. in case the svi programmed reference plus the offset set through the ovrspd command exceed this value, the reference for the regulation is clamped to 2.8 v. the maximum possible output voltage for nb se ction is internally limited by the maximum offset achievable for nb section that is +600 mv over the svi programmed reference. once the controller acknowledges the command and recognizes the ovrspd command, the reference will step up or down until reaching the target offset performing a on-the-fly vid transition. in case a new overspeed command is issued while the output voltage is not yet stabilized (i.e. the reference is still stepping to th e target), the target is updated according to the new offset defined. the command addresses both sections through two separate bits in the command code (?cn? bits - see t a ble 12 ). by asserting the corresponding bit, the subsequent data stream will apply to the identified se ction. asserting both bits (?cn? = 11b) will address both sections. cn = 00b will be ignored regardless of the data stream provided. ?cn? = 10b and ?cn? = 01b allow to address only core or only nb section respectively. 010 [1:4] xxxx [5:6] k drpnb [7:8] k drp drp_adj: droop function adjustment. modifies the slope of the output voltage implemented th rough the droop function. [1:4]: ignored [5:6]: k drpnb . defines the k drp factor for nb section. [7:8]: k drp . defines the k drpnb factor for core section. default value is k drpx = 1/4 for both sections. see t a ble 16 for details about drp_adj codification and s ection 7.3 and s ection 7.6 for loadline definition. 011 [1:3] xxx [4:5] dpmth [6] psi_a [7] psi_en [8] dpm_on power m a n a gement fl a gs: set of three flags to define power management actions of the controller. [1:3]: ignored [4:5]: dpm thresholds. default is 00b. [6] psi_a: p s i a ction . it defines the action to take when psi_l flag is asserted by svi bus. the same action is considered by dpm. send 0b to work in single phase (default) or 1b to work at two phases. [7] psi_en: p s i en a ble . it enables or disables the psi management. set to 1b (default) to manage psi_l according to psi_a or set to 0b to ignore psi_l flag sent through svi bus. [8] dpm_on: dyn a mic ph a se m a n a gement . it enables or disables the dpm mode. set to 1b to enable dpm or set to 0b (default) to disable it. when enabled dpm acts automatically cutting phases according to psi action flag at light load. see s ection 6.2 for details about dpm. table 12. power manager i 2 c command phase and data stream command code [4:6] data stream [1:8] description
power manager i2c L6717 30/56 doc id 17326 rev 1 see t a ble 12 and t a ble 13 for details about the codification of the command and the data stream. 6.1.2 overvoltage threshold adjustment (ov_set) this command allows to adjust the overvoltage threshold independently for core and nb sections. the default ovp threshold value of +250 mv over the reference is adjustable, in 200 mv steps up to +850 mv above the reference for core and +650 mv above the reference for nb. see t a ble 12 and t a ble 14 for details about the codification of the command and the data stream. table 14. ovp_set command - threshold codification 6.1.3 switching frequency adjustment (fsw_adj) this command allows to adjust the switching frequency for the system in +/-10% steps across the main level defined by the osc pin. switching frequency margining may benefit the system from the thermal and performance point of view. see t a ble 12 and t a ble 15 for details about the codification of the command and the data stream. table 13. ovrspd command - offset codification (1) (2) 1. offset is added with an otf vid transition above the programmed vid. 2. maximum regulated output voltage is in ternally limited to 2.8v maximum: regardless the offset over vid reference the ic does not allow to reach an higher voltage. data stream [4:8] offset to reference [v] data stream [4:8] offset to reference [v] data stream [4:8] offset to reference [v] data stream [4:8] offset to reference [v] 00000 0.00 01000 0.40 10000 0.80 11000 1.20 00001 0.05 01001 0.45 10001 0.85 11001 1.25 00010 0.10 01010 0.50 10010 0.90 11010 1.30 00011 0.15 01011 0.55 10011 0.95 11011 1.35 00100 0.20 01100 0.60 10100 1.00 11100 1.40 00101 0.25 01101 0.65 10101 1.05 11101 1.45 00110 0.30 01110 0.70 10110 1.10 11110 1.50 00111 0.35 01111 0.75 10111 1.15 11111 1.55 data stream [5:6] and [7:8] ovp threshold [v] 00 +250mv (default) 01 +450mv 10 +650mv 11 +850mv core / +650mv for nb
L6717 power manager i2c doc id 17326 rev 1 31/56 6.1.4 droop function adjustment (drp_adj) this command allows to adjust the slope for the output voltage load line once the external components are defined by modifying the k drp and k drpnb parameters defined in s ection 7.3 and s ection 7.6 . see t a ble 12 and t a ble 16 for details about the codification of the command and the data stream. 6.1.5 power management flags this command allows to set several flags to configure L6717 power management. the flags allows to define: ? psi_a. this flag defines phase shedding strategy adopted when cpu asserts psi_l by svi bus. set psi_a = 0b (default) to program the device to work in single phase or set psi_a = 1b to program two phase mode. the selected strategy applies also to dpm mode. see s ection 5.4.3 for details about psi management and light-load efficiency optimizations. see s ection 6.2 for details about dpm. ? psi_en. this flag defines whether to enable or not the psi_l management. default is to manage psi_l flag assertion through svi bus (psi_en = 1b). ? dpm_on. this flag defines whether to enable or not the dpm mode. the strategy adopted by dpm is defined through the psi_a flag. see s ection 6.2 for details about dpm. dpm is disabled by default (dpm_on = 0h). ? dpmth. allow to program up to 4 different strategies for dpm mode by properly adjusting the v dpm threshold. see s ection 6.2 for details about dpm. see t a ble 12 and t a ble 17 for details about the codification of the command and the data stream. table 15. fsw_adj command - switching frequency adjustment codification data stream [6:8] fsw adjustment data stream [6:8] fsw adjustment 000 reset to frequency programmed by osc 100 reset to frequency programmed by osc 001 -10% 101 +10% 010 -20% 110 +20% 011 ignored 111 ignored table 16. drp_adj command - droop function adjustment codification data stream [5:6] and [7:8] drp adjustment k drpnb [5:6] and k drp [7:8] 00 1/4 01 1/2 10 ignored 11 droop disabled
power manager i2c L6717 32/56 doc id 17326 rev 1 6.2 dynamic phase management (dpm) dynamic phase management allows to adjust the number of working phases according to the delivered current still maintaining th e benefits of the mu ltiphase regulation. phase number is reduced by monitoring the voltage level across ilim pin: L6717 reduces the number of working phase according to the strategy defined by the psi_a flag when the voltage across ilim pin is lower than v dpm . when the load current increases the phase number is restored to the original value as soon as the voltage across ilim pin exceeds v dpm . v dpm is selected through the dpmth command. see s ection 6.1 . the current at which the transition happens (i dpm ) can be estimated as: v dpm thresholds are defined as a percentage of the voltage on ilim pin corresponding to the thermal design current of the application. 1.8v on ilim pin corresponds to 100% of the load and dpm threshold are defined as a percentage of 1.8v (see t a ble 18 for details). an hysteresis is provided for each threshold in order to avoid multiple dpm actions triggering in steady load conditions. dpm is disabled by default: soft-start is performed with all the available phases. table 17. power management flags data stream bit flag description [1:3] n/a ignored. [4:5] dpmth dpm threshold. allow to define 4 different values for v dpm . see s ection 6.2 for code/thresholds correspondence. [6] psi_a 0b (default): ic working in single phase when psi_l asserted. 1b:ic working in two phase when psi_l asserted. [7] psi_en 0b: psi_l flag in svi ignored. 1b (default): psi_l flag in svi monitored and phase dropping enabled according to psi_a. [8] dpm_on 0b (default): dpm disabled. 1b: dpm enabled. table 18. v dpm thresholds code v dpm (i lim rising) v dpm (i lim falling) 00 (default) 20% 15% 01 25% 20% 10 30% 25% 11 35% 30% i dpm v dpm r ilim -------------- - r g dcr ------------- ? =
L6717 power manager i2c doc id 17326 rev 1 33/56 when the soft start is over and once pwrgood rise to logic ?1?, L6717 can receive commands on power manager i 2 c bus to enable dpm. once dpm is enabled, L6717 starts monitoring the ilim voltage: the voltage is compared with the internal v dpm threshold defining the current level to trigger the number modification. dpm is reset in particular conditions: ? during otf vid transition issued by the cpu; ? when ltb technology ? detects a load transient. after being reset, dpm is re-enabled with a proper delay: the phase number is again defined according to the ilim pin voltage with respect v dpm . delay in the intervention of dp m can be adjusted by properly sizing the filer across ilim pin. increasing the capacitance results in increased delay in the dpm intervention.
output voltage positioning L6717 34/56 doc id 17326 rev 1 7 output voltage positioning output voltage positioning is performed by selecting the controller operative-mode ( s vi, pvi and v_fix ) and by programming the droop function and offset to the reference of both the sections (see figure 9 ). the controller reads the current delivered by each section by monitoring the voltage drop across the dcr inductors. the current (i droop / i droop_nb ) sourced from the fb / nb_fb pin, directly proportional to the read current, causes the related section output voltage to vary according to the external r fb / r fb_nb resistor so implementing the desired load-line effect. L6717 embeds a dual remote-sense buffer to sense remotely the regulated voltage of each section without any additional external components. in this way, the output voltage programmed is regulated compensating for board and socket losses. keeping the sense traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. figure 9. voltage positioning 1.2v r os scl/os core_reference fb comp vsen fbg r f c f r fb to vdd_core (remote sense) k drp i droop -i os i os core protection monitor from svi dac... nb_reference nb_fb nb_comp nb_vsen nb_fbg r f_nb c f_nb r fb_nb to vdd_nb (remote sense) k drpnb i droop_nb nb protection monitor from dac... core section voltage positioning nb section voltage positioning operative only when power manager i2c disabled offset from power manager i2c (active when enabled) clamp to 2.8v max
L6717 output voltage positioning doc id 17326 rev 1 35/56 7.1 core section - phase # programming core section implements a flexible 2 to 4 interleaved-phase converter. to program the desired number of phase, simply short to gnd the pwmx signal that is not required to be used according to t a ble 19 . for three phase operation, short pwm4 to gnd while for two phase operation, short pwm3 and pwm4 to gnd. caution: for the disabled phase(s), the current reading pins need to be properly connected to avoid errors in current-sharing and voltage-positioning: csxp needs to be connected to the regulated output voltage while csxn needs to be connected to csxp through the same r g resistor used for the active phases. see figure 2 and figure 3 for details in 3-phase and 2- phase connections. table 19. core section - phase number programming 7.2 core section - current re ading and current sharing loop L6717 embeds a flexible, fully-differential current sense circuitry for the core section that is able to read across inductor parasitic resi stance or across a sense resistor placed in series to the inductor element. the fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy. the trans-conductance ratio is issued by the external resistor r g placed outside the chip between csxn pin toward the reading points. the current sense circuit always tracks the current information, the pin csxp is used as a reference keeping the csxn pin to this volt- age. to correctly reproduce the inductor current an r-c filtering network must be introduced in parallel to the sensing element. the current that flows from the csxn pin is then given by the following equation (see figure 10 ): considering now to match the time constant between the inductor and the r-c filter applied (time constant mismatches caus e the introduction of poles into the current reading network causing instability. in addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance) it results: r g resistor is typically designed in order to have an information current i infox in the range of about 35 a (i octh ) at the oc threshold. phase number pwm3 pwm4 2gnd gnd 3 to driver gnd 4 to driver to driver i csxn dcr r g ------------- 1 s l dcr ? ? + 1src ?? + ------------------------------------- - i ? phasex ? = l dcr ------------- rc i csxn r l r g ------- - i phasex ? = ? ? i infox ==
output voltage positioning L6717 36/56 doc id 17326 rev 1 figure 10. current reading the current read through the csxp / csxn pairs is converted into a current i infox propor- tional to the current delivered by each phase and the information about the average current i avg = i infox / n is internally built into the device (n is the number of working phases). the error between the read current i infox and the reference i avg is then converted into a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase. 7.3 core section - defining load-line L6717 introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor esr in the load transient. introducing a dependence of the output voltage on the load current, a static error, proportional to the output current, causes the output voltage to vary according to the sensed current. figure 10 shows the current sense circuit used to implement the load-line. the current flow- ing across the inductor(s) is read through th e r - c filter across csxp and csxn pins. r g programs a trans-conductance gain and generates a current i csx proportional to the current of the phase. the sum of the i csx current, with proper gain defined by the drp_adj com- mand (k drp ), is then sourced by the fb pin (k drp i droop ). r fb gives the final gain to pro- gram the desired load-line slope ( figure 9 ). time constant matching between the inductor (l / dcr) and the current reading filter (rc) is required to implement a real equivalent output impedance of the system so avoiding over and/or under shoot of the output voltage as a consequence of a load transient. see s ection 7.2 . the output characteristic vs. load current is then given by: where r ll is the resulting load-line resistance implemented by the core section. k drp value is determined by the power manager i 2 c and its default value is 1/4. r fb resistor can be then designed according to the r ll specifications and drp_adj setting as follow: see s ection 6.2 for details about drp_adj command. lx csxp csxn dcr x r c r g i phasex inductor dcr current sense i csxn =i infox v out v core vid r fb k drp i droop ?? ? vid k drp r fb dcr r g ------------- i out ?? ? ? vid r ll i out ? ? == = r fb r ll k drp ------------- r g dcr ------------- ? =
L6717 output voltage positioning doc id 17326 rev 1 37/56 7.4 core section - analog off set (optional - i2cdis = 3.3 v) when power manager i 2 c is disabled (i2cdis = 3.3 v), L6717 still provide the way to add positive/negative offset to the core section. in this particular conditions, the pin scl/os becomes a virtual ground and allows programming a positive/negative offset (v os ) for the core section output voltage by connecting a resistor r os to sgnd/vcc. the pin is inter- nally fixed at 1.240 v (2.0 v in case of negative offset, r os tied to vcc) so a current is pro- grammed by connecting the resistor r os between the pin and sgnd/vcc: this current is mirrored and then properly sunk/sourced from the fb pin as shown in figure 9 . output volt- age is then programmed as follow: offset resistor can be designed by considering the following relationship (r fb is be fixed by the droop effect): (positive offset) (negative offset) caution: offset implementation is optional, in case it is not desired, simply short the pin to gnd. note: in the a bove formul a s, r fb h a s to be considered being the tot a l resist a nce connected between fb pin a nd the regul a ted volt a ge. k drp h a s to be considered h a ving its def a ult v a lue since power m a n a ger i 2 c is dis a bled. 7.5 nb section - current reading nb section performs the same differential current reading across dcr as the core sec- tion. according to s ection 7.2 , the current that flows from the nb_csn pin is then given by the following equation (see figure 10 ): r g_nb resistor is typically designed according to the oc threshold. see s ection 8.4 for details. 7.6 nb section - defining load-line this method introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor esr in the load transient. introducing a depen- dence of the output voltage on the load current, a static error, proportional to the output cur- rent, causes the output voltage to vary according to the sensed current. figure 10 shows the current sense circuit used to implement the load-line. the current flow- ing across the inductor dcr is read through r g_nb . r g_nb programs a trans-conductance gain and generates a current i droop_nb proportional to the current delivered by the nb section that is then sourced from the nb_fb pin with proper gain defined by the drp_adj v core vid r fb k drp i droop ? i os ? () ? ? = r os 1.240v v os ------------------ - r fb ? = r os vcc 2.0v ? v os ------------------------------- - r fb ? = i nb_csn dcr(nb) r g_nb ------------------------ - i nb ? i droop_nb ==
output voltage positioning L6717 38/56 doc id 17326 rev 1 command (k drpnb ). r fb_nb gives the final gain to program the desired load-line slope ( figure 9 ). the output characteristic vs. load current is then given by: where r ll_nb is the resulting load-line resistance implemented by the nb section. k drpnb value is determined by the power manager i 2 c and its default value is 1/4. r fb_nb resistor can be then designed according to the r ll_nb specifications and drp_adj setting as follow: 7.7 on-the-fly vid transitions L6717 manages on-the-fly vid transitions that allow the output voltage of both sections to modify during normal device operation for cpu power management purposes. ov, uv and pwrgood signals are masked during every otf-vid transition and they are re-activated with a 16 clock cycle delay to prevent from false triggering. when changing dynamically the regulated voltage (otf-vid), the system needs to charge or discharge the output capacitor accordingly. this means that an extra-current i otf-vid needs to be delivered (especially when increasing the output regulated voltage) and it must be considered when setting the over current threshold of both the sections. this current results: where dv out / dt vid depends on the operative mode (3mv/ sec. in svi or externally driven in pvi). overcoming the oc threshold during the dynami c vid causes the device latch and disable. dynamic vid transition is managed in different ways according to the device operative mode: pvi mode. L6717 checks for vid code modifications (see figure 11 ) on the rising-edge of an internal additional otfvid-clock and wait s for a confirmation on the following falling edge. once the new code is stable, on the next rising edge, the reference starts stepping up or down in lsb increments every two otfvid-clock cycle until the new vid code is reached. during the transition, vid code changes are ignored; the device re-starts monitoring vid after the transiti on has finished on the next rising-edge available. otfvid-clock frequency (f otfvid ) is 500 khz. if the new vid code is more than 1 lsb di fferent from the previous, the device will execute the transition stepping the refere nce with the otfvid-clock frequency f otfvid v out_nb =vid r fb_nb k drpnb i droop_nb ?? ? vid r fb_nb k drpnb dcr nb () r g_nb --------------------------- i out ?? ? ? vid r ll_nb i out_nb ? ? = r fb_nb r ll_nb k drpnb -------------------- - r g_nb dcr nb () --------------------------- ? = i otf-vid c out dv out dt vid ------------------ ? =
L6717 output voltage positioning doc id 17326 rev 1 39/56 until the new code has reached. the output voltage rate of change will be of 12.5 mv / 4 sec. = 3.125 mv/ sec. figure 11. pvi mode - on-the-fly vid transitions svi mode. as soon as the controller receives a new valid command to set the vid level for one (or both) of the two sections, the reference of the involved section steps up or down according to the target-vid with a 3 mv/ sec. slope (typ). until the new vid code is reached. if a new valid command is issued during the transition, the device updates the target- vid level and performs the on-the-fly transition up to the new code. pre-pwrok metal-vid otf-vid are not managed in this case because the pre- pwrok met a l vid are stored after en is asserted. v_fix mode. L6717 checks for svc/svd modifications and, once the new code is stable, it steps the reference of both sections up or down according to the target-vid with a 3 mv/ sec. slope (typ). until the new vid code is reached. ov, uv and pwrgood are masked during the transition and re-activated with a 16 clock cycle delay after the end of the transition to prevent from false triggering. t otfvid x 4 step vid transition t t t vid sampled vid sampled vid sampled ref moved (1) ref moved (2) ref moved (3) ref moved (4) vid stable vid [0:5] int. reference v out t sw vid sampled vid sampled ref moved (1) ref moved (1) ref moved (1) vid sampled vid sampled 4 x 1 step vid transition t vid vid sampled vid sampled vid sampled vid sampled vid sampled vid stable vid stable vid stable ref moved (1) vid sampled vid sampled vid stable vid sampled vid sampled vid sampled t otfvid clock vout slope controlled by internal otfvid-clock oscillator vout slope controlled by external driving circuit (t vid )
output voltage positioning L6717 40/56 doc id 17326 rev 1 7.8 soft-start L6717 implements a soft-start to smoothly charge the output filter avoiding high in-rush cur- rents to be required to the input power supply. in svi mode, soft-start time is intended as the time required by the device to set the output voltages to the pre-pwrok met a l vid . during this phase, the device increases the reference of the enabled section(s) from zero up to the programmed reference in closed loop regulation. soft-start is implemented only when vcc is above uvlo threshold and the en pin is set free. see s ection 5 for details about the svi interface and how svc/svd are interpreted in this phase. at the end of the digital soft-start, pwrgood signal is set free. protections are active during this phase as follow: ? undervoltage is enabled when the reference voltage reaches 0.5 v. ? overvoltage is always enabled according to the programmed threshold (by r ovp ). ? fb disconnection is enabled. reference is increased with fixed dv/dt; soft-start time depends on the programmed voltage as follow: figure 12. system start-up: svi (left) and pvi (right) 7.8.1 ls-less start-up in order to avoid any kind of negative undershoot on the load side during start-up, L6717 performs a special sequence in enabling the drivers for both sections: during the soft-start phase, the ls mosfet is kept off (pwmx set to hiz and endrv = 0) until the first pwm pulse. after the first pwm pulse, the pwmx outputs switches between logic ?0? and logic ?1? and endrv are set to logic ?1?. this particular sequence avoids the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output especially when exiting from a core-off state. low-side mosfet turn-on is masked only from the control loop point of view: protections are still allowed to turn-on the low-side mo sfet in case of over voltage if needed. t ss ms [] target_vid 2.56 ? =
L6717 output voltage monitoring and protections doc id 17326 rev 1 41/56 8 output voltage monitoring and protections L6717 monitors the regulated voltage of both sections th rough pin vsen and nb_vsen in order to manage ov, uv and pwrgood. the device shows different thresholds when in different operative conditions but the behavior in response to a protection event is still the same as described below. protections are active also during soft-start (see s ection 7.8 ) while they are masked during otf-vid transitions with an additional delay to avoid false triggering. table 20. L6717 protection at a glance 8.1 programmable overvoltage (i2dis = 3.3 v) when power manager i 2 c is disabled, L6717 prov ides the possibility to adjust ov threshold (common for both sections) through the sda/ovp pin. connecting the pin to the center tap of a voltage divider from 3.3 v to sgnd, the ovp threshold becomes the voltage present at the pin. the ovp threshold results: L6717 section core north bridge overvoltage (ov) s vi / pvi: +250mv above reference, programmable by power manager i 2 c bus. i2cdis = 3.3v: programmable through sda/ovp pin. v_fix: fixed to 1.8v. action: ic latch; ls=on & pwmx = 0 (if applicable); other section (svi only): hiz; flt driven high. undervoltage (uv) vsen, nb_vsen = vid -400mv. active after ref > 500mv action: ic latch; both sections hiz; flt driven high. pwrgood pwrgood is the logic and between inte rnal core and nb pgood in svi mode while is the core section pgood in pvi mode. each pgood is set to zero when the related voltage falls below the programmed reference -250mv. action: section(s) continue switching, pwrgood driven low. vsen, nb_vsen disconnection set when vsen > cs1n +600mv. action: uv-like set when vsen > nb_csn +600mv. action: uv-like (svi only) fbg, nb_fbg disconnection internal comparator across the opamp to recover from gnd losses. action: uv-like over current (oc) current monitor across inductor dcr. dual protection, per-phase and average. action: uv-like current monitor acro ss inductor dcr. constant current. action: uv-like on-the-fly vid protections masked with the exception of oc with additional 16 clock delay to prevent from false triggering (both svi and pvi). ovp th 3.3 r ovpl r ovph r + ovpl ------------------------------------------ - ? =
output voltage monitoring and protections L6717 42/56 doc id 17326 rev 1 figure 13. analog ovp threshold when the voltage sensed by vsen and/or nb_ vsen overcomes the ov threshold, the con- troller: ? permanently sets the pwm of the involved section to zero keeping endrv of that section high in order to keep all the low-side mosfets on to protect the load of the section in ov condition. ? permanently sets the pwm of the non-involved section to hiz while keeping endrv of the non-involved section low in order to realize an hiz condition of the non-involved section. ? drives the osc/ flt pin high. ? power supply or en pin cycling is required to restart operations. filter ovp pin with 1nf(typ) to sgnd. 8.2 feedback disconnection L6717 provides both core and nb sections with fb disconnection protection. this feature acts in order to stop the device from regulating dangerous voltages in case the remote sense connections are left floating. the protection is available for both the sections and operates for both the positive and negative sense. according to figure 14 , the protection works as follow: core section: positive sense is performed monitoring th e core output voltage through both vsen and cs1n. as soon as cs1n is more th an 600 mv higher than vsen, the device latches in hiz. flt pin is driven high. a 30 a pull-down current on the vsen forces the device to detect this fault condition. negative sense is performed monitoring the internal opamp used to recover the gnd losses by comparing its output and the internal reference generated by the dac. as soon as the difference between the output and the input of this opamp is higher than 500 mv, the device latches in hiz. flt pin is driven high. nb section (svi only) positive sense is performed monitoring th e nb output voltage through both nb_vsen and nb_csn. as soon as nb_csn is more than 600 mv hig her than nb_vsen, the device latches in hiz. flt pin is driven high. a 30 a pull-down current on the nb_vsen forces the device to detect this fault condition. negative sense is performed monitoring the internal opamp used to recover the gnd losses by comparing its output and the internal reference generated by the dac. as sda/ovp r ovph analog ovp setting (i2c disabled) 3v3 r ovpl c ovp
L6717 output voltage monitoring and protections doc id 17326 rev 1 43/56 soon as the difference between the output and the input of this opamp is higher than 500mv, the device latches in hiz. flt pin is driven high. to recover from a latch condition, cycle vcc or en. figure 14. fb disconnection protection 8.3 pwrgood it is an open-drain signal set free after the soft-start sequence has finished; it is the logic and between the internal core and nb pgood (or just the core pgood in pvi mode). it is pulled low when the output voltage of one of the two sections drops 250 mv below the programmed voltage. it is masked during on-the-fly vid transitions as well as when the core section is set to off (from svi bus) while the nb section is still operative. 8.4 overcurrent the overcurrent threshold has to be programmed to a safe value, in order to be sure that each section doesn't enter oc during normal operation of the device. this value must take into consideration also the extra current needed during the otf-vid transition (i otf-vid ) and the process spread and temperature variations of the sensing elements (inductor dcr). moreover, since also the internal threshold sp reads, the design has to consider the mini- mum/maximum values of the threshold. considering the reading method, the two sections will show different behaviors in oc. 8.4.1 core section L6717 performs two different oc protections for the core section: it monitors both the total current and the per-phase current and allows to set an oc threshold for both. ? per-phase oc. maximum information current per-phase (i infox ) is internally limited to 35 a. this end-of-scale current (i oc_th ) is compared with the information current generated for each phase (i infox ). if the current information for the single phase exceed the end-of-scale current (i.e. if i infox > i oc_th ), the device will turn-on the ls mosfet until the threshold is re-crossed (i.e. until i infox < i oc_th ). ? total current oc. ilim pin allows to define a maximum total output current for the system (i oc_tot ). i lim current is sourced from the ilim pin (not altered by drp_adj command). by connecting a resistor r ilim to sgnd, a load indicator with 2.5 v (v oc_tot ) end-of- core_reference fb comp vsen fbg r f c f r fb to vdd_core (remote sense) from dac... core and nb section - vsen and fbg disconnection 500mv fbg disconnected cs1- 30 a 600mv
output voltage monitoring and protections L6717 44/56 doc id 17326 rev 1 scale can be implemented. when the voltage present at the ilim pin crosses v oc_tot , the device detects an oc and immediately latches with all the mosfets of all the sections off (hiz). typical design considers the intervention of the total current oc before the per-phase oc, leaving this last one as an extreme-protection in case of hardware failures in the external components. typical design flow is the following: ? define the maximum total output current (i oc_tot ) according to system requirements ? design per-phase oc and r g resistor in order to have i infox = i oc_th (35 a) when i out is about 10% higher than the i oc_tot current. it results: where n is the number of phases and dcr th e dc resistance of the inductors. r g should be designed in worst-case conditions. ? design the total current oc and r ilim in order to have the ilim pin voltage to v oc_tot at the desired maximum current i oc_tot . it results: where v oc_tot is typically 2.5v and i oc_tot is the total current oc threshold desired. ? adjust the defined values according to bench-test of the application. ? an additional capacitor in parallel to r ilim can be considered to add a delay in the protection intervention. note: wh a t previously listed is the typic a l design flow. custom design a nd specific a tions m a y require different settings a nd r a tios between the per-ph a se oc threshold a nd the tot a l current oc threshold. applic a tions with huge ripple a cross inductors m a y be required to set per-ph a se oc to v a lues different th a n 110%: design flow should be modified a ccordingly. note: drp_adj comm a nd from power m a n a ger i 2 c does not a lter the current inform a tion used for per-ph a se oc a nd tot a l current oc. r g 1.1 i oc_tot ? () dcr ? ni ? octh -------------------------------------------------------- = r ilim v oc_tot r g ? i oc_tot dcr ? -------------------------------------- - = i lim dcr r g ------------- i out ? = ?? ??
L6717 output voltage monitoring and protections doc id 17326 rev 1 45/56 8.4.2 nb section nb section performs per-phase over current: its maximum information current (i info_nb ) is internally limited to i octh_nb (35 a typ). if the current information for the nb phase exceeds the end-of-scale current (i.e. if i info_nb > i octh_nb ), the device will turn-on the low-side mosfet, also skipping clock cycles, until the threshold is re-crossed (i.e. until i info_nb < i octh_nb ). after exiting the oc condition, the low-side mosfet is turned off and the high-side is turned on with a duty cycle driven by the pwm comparator. design r g_nb resistor in order to have i droop_nb = i octh_nb (35 a) at the i oc_nbmax current. it results: note: drp_adj comm a nd from power m a n a ger i 2 c does not a lter the current inform a tion used for per-ph a se oc. r gnb i oc_nbmax dc r ? i octh_nb ------------------------------------------ - =
main oscillator L6717 46/56 doc id 17326 rev 1 9 main oscillator the controller embeds a dual-osc illator: one section is used fo r the core and it is a multi- phase programmable oscillator m anaging equal phase-shift among all phases and the other section is used for the nb section. phase-shift between the core and nb ramps is automatically adjusted according to the core phase # programmed. the internal oscillator generates the tria ngular waveform for the pwm charging and discharging with a constant current an internal capacitor. the switching frequency for each channel, f sw , is internally fixed at 200 khz: the resulting switching frequency for the core section at the load side results in being multiplied by n (number of configured phases). the current delivered to t he oscillator is typically 20 a (corresponding to the free running frequency f sw =200 khz) and it may be varied using an external resistor (r osc ) typically connected between the osc pin and sgnd. since the osc pin is fixed at 1.240 v, the frequency is varied proportionally to the current sunk from the pin considering the internal gain of 9.1 khz/ a (see figure 15 ). connecting r osc to sgnd the frequency is increased (current is sunk by the pin), according to the following relationships: connecting r osc to a positive voltage (recommended 3.3 v rail) the frequency is reduced (current is injected into the pin), a ccording to the following relationships: where +v is the positive voltage which the r osc resistor is connected. figure 15. r osc vs. switching frequency f sw 200khz 1.240v r osc ------------------ - 9.1 khz a ---------- - ? + = f sw 200khz +v 1.240 ? r osc ---------------------------- 9.1 khz a ---------- - ? ? = fsw vs. rosc 75 125 175 225 275 325 375 425 0 50 100 150 200 250 300 350 400 450 rosc [kohm] fsw [khz] rosc+ (to sgnd) rosc- (to 3v3)
L6717 high current embedded drivers doc id 17326 rev 1 47/56 10 high current embedded drivers L6717 provides high-current driving control for core and nb sections. the driver for the high-side mosfet use bootx pin for supply and phasex pin for return. the driver for the low-side mosfet use the vccdr pin for supply and gnd pin for return. the embedded driver embodies an anti-shoot-through and adaptive dead-time control to minimize low-side body diode conduction time ma intaining good efficiency saving the use of schottky diodes: when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches about 2 v, the low-side mosfet gate drive voltage is suddenly applied. when the low-side mosfet turns off, the voltage at lgate pin is sensed. when it drops below about 1 v, the high-side mosfet gate drive voltage is suddenly applied. if the current flowing in the inductor is negative, the source of high-side mosfet will never drop. to allo w the low-side mosfet to tu rn-on even in this case, a watchdog controller is enabled: if the source of the high-side mosfet doesn't drop, the low-side mosfet is switched on so allowing the negative current of the inductor to recirculate. this mechanism allows the system to regulate even if the current is negative. 10.1 boot capacitor design bootstrap capacitor needs to be designed in order to show a negligible discharge due to the high-side mosfet turn-on. in fact it must give a stable voltage supply to the high-side driver during the mosfet turn-on also minimizing the power dissipated by the embedded boot diode. figure 16 gives some guidelines on how to select the capacitance value for the bootstrap according to the desired discharge and depending on the selected mosfet. to prevent bootstrap capacitor to extra-charge as a consequence of large negative spikes, an external series resistance r boot (in the range of few ohms) may be required in series to boot pin. figure 16. bootstrap capacitor design 0.0 0.5 1.0 1.5 2.0 2.5 0 102030405060708090100 high-side mosfet gate charge [nc] boot cap discharge [v] cboot = 47nf cboot = 100nf cboot = 220nf cboot = 330nf cboot = 470nf 0 500 1000 1500 2000 2500 0.0 0.2 0.4 0.6 0.8 1.0 boot cap delta voltage [v] bootstrap cap [uf] qg = 10nc qg = 25nc qg = 50nc qg = 100nc
high current embedded drivers L6717 48/56 doc id 17326 rev 1 10.2 power dissipation it is important to consider the power that the device is going to dissipate in driving the exter- nal mosfets in order to avoid overcoming the maximum junction operative temperature. two main terms contribute in the device power dissipation: bias power and drivers' power. device power (p dc ) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow: drivers' power is the power needed by the driver to continuously switch on and off the external mosfets; it is a function of the switching frequency and total gate charge of the selected mosfets. it can be quantified considering that the total power p sw dissipated to switch the mosfets dissipated by three main factors: external gate resistance (when present), intrinsic mosfet resistance and intrinsi c driver resistance. this last term is the important one to be determined to calculate the device power dissipation. the total power dissipated to switch the mosfets for each phase featuring embedded driver results: where q ghsx is the total gate charge of the hs mosfets and q glsx is the total gate charge of the ls mosfets for both core and nb sections (only phase1 and phase2 for core section); vbootx is the driving voltage for the hsx mosfets. p dc v cc i cc v vccdr i vccdr ? + ? = p swx f sw q glsx vccdr ? q ghsx vbootx ? + () ? =
L6717 system control loop compensation doc id 17326 rev 1 49/56 11 system control loop compensation the device embeds two separate and independent control loops for core and nb section. the control loop for nb section is a simple volt age-mode control loop with (optional) voltage positioning featured when droop pin is shorted with fb. the control loop for the core section also features a current-sharing loop to equalize the current carried by each of the configured phases. the core control system can be modeled with an equivalent single-phase converter whose only difference is the equivalent inductor l/n (where each phase has an l inductor and n is the number of the configured phases). see figure 17 . figure 17. equivalent control loop for nb and core sections this means that the same analysis can be used for both the sections with the only exception of the different equivalent inductor value (l=l nb for nb section and l=l core /n for the core section) and the current reading gain (dcr/r g_nb for nb section and dcr/r g for the core section). the control loop gain results (obtained opening the loop after the comp pin): where: r ll is the equivalent output resistance determined by the droop function; z p (s) is the impedance resulting by the parallel of the output capacitor (and its esr) and the applied load r o ; z f (s) is the compensation network impedance; z l (s) is the equivalent inductor impedance; a(s) is the erro r amplifier gain; is the pwm transfer function. the control loop gain for each section is designed in order to obtain a high dc gain to minimize static error and to cross the 0db axes with a constant -20 db/dec. slope with the desired crossover frequency t . neglecting the effect of z f (s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (lc filter resonance lc ) and the zero ( esr ) is fixed by esr and the droop resistance. ref nb_comp nb_vsen nb_fbg r f_nb c f_nb r fb_nb pwm l nb esr_nb c o_nb r o_nb d v nb_comp v out_nb z f (s) z fb (s) k drpnb i droop_nb vid_nb v nb_comp ref comp vsen fbg r f c f r fb pwm l core /n esr c o r o d v comp v out z f (s) z fb (s) k drp i droop vid_core v comp fb nb_fb g loop s () pwm z f s () r ll z p s () + () ?? z p s () z l s () + [] z f s () as () -------------- 1 1 as () ----------- - + ?? ?? r fb ? + ? ------------------------------------------------------------------------------------------------------------------- ? = pwm 3 5 -- - v in v osc ------------------ - ? =
system control loop compensation L6717 50/56 doc id 17326 rev 1 figure 18. control loop bode diagram and fine tuning (not in scale) to obtain the desired shape an r f -c f series network is considered for the z f (s) implementation. a zero at f =1/r f c f is then introduced together with an integrator. this integrator minimizes the static error while placing the zero f in correspondence with the l- c resonance assures a simple -20 db/dec. shape of the gain. in fact, considering the usual value for the output filter, the lc resonance results to be at frequency lower than the above reported zero. compensation network can be simply designed placing f = lc and imposing the cross- over frequency t as desired obtaining (always considering that t might be not higher than 1/10th of the switching frequency f sw ): 11.1 compensation network guidelines the compensation network design assures to having system response according to the cross-over frequency selected and to the output filter considered: it is anyway possible to further fine-tune the compensation network modifying the bandwidth in order to get the best response of the system as follow (see figure 18 ): ? increase r f to increase the system bandwidth accordingly; ? decrease r f to decrease the system bandwidth accordingly; ? increase c f to move f to low frequencies increasing as a consequence the system phase margin. having the fastest compensation network gives not the confidence to satisfy the requirements of the load: th e inductor still limits the maxi mum di/dt that the system can afford. in fact, when a load transient is applied, the best that the controller can do is to ?saturate? the duty cycle to its maximum (d max ) or minimum (0) value. the output voltage dv/dt is then limited by the inductor charge / discharge time and by the output capacitance. in particular, the most limiting transition corresponds to the load removal since the inductor results being discharged only by v out (while it is charged by d max v in -v out during a load appliance). db z f (s) g loop (s) k lc = f esr t r f [db] db z f (s) g loop (s) k lc = f esr t r f [db] r f c f r f r fb v osc ? v in --------------------------------- - 3 5 -- - t l nr ll esr + () ? ------------------------------------------ - ?? ? = c f c o l ? r f ------------------- - =
L6717 ltb technology ? doc id 17326 rev 1 51/56 12 ltb technology ? lt b te c h n o l o gy ? further enhances the performances of dual-edge asynchronous systems by reducing the system latencies and immediatel y turning on all the phases to provide the correct amount of energy to the load. by properly designing the ltb network as well as the ltb gain, the undershoot and the ring-back can be minimized also optimizing the output capacitors count. ltb technology ? applies only to the core section. lt b te c h n o l o gy ? monitors the output voltage through a dedicated pin detecting load- transients with selected dv/dt, it cancels the interleaved phase-shift, turning-on simultaneously all phases. it then implements a parallel, independent loop that reacts to load-transients bypassing e/a latencies. lt b te c h n o l o gy ? control loop is reported in figure 19 . figure 19. ltb technology ? control loop (core section) the ltb detector is able to detect output load transients by coupling the output voltage through an r lt b - c lt b network. after detecting a load transient, the ltb ramp is reset and then compared with the comp pin level. the resulting duty-cycle pr ogrammed is then or- ed with the pwmx signal of each phase by-pas sing the main control loop. all the phases will then be turned-on together and the ea latencies results bypassed as well. sensitivity of the load transient detector can be programmed in order to control precisely both the undershoot and the ring-back. r lt b - c lt b is designed according to the output voltage deviation dv out which is desired the controller to be sensitive as follow: lt b te c h n o l o gy ? design tips. ? decrease r lt b to increase the syste m sensitivity making the system sensitive to smaller dv out . ? increase c lt b to increase the syste m sensitivity making the system sensitive to higher dv/dt. ref fb comp vsen fbg r f c f r fb pwm l/n esr c o r o d v comp v out z f (s) z fb (s) vid v comp c h c fb lt b monitor r lt b c lt b pwm_boost ltb ramp ltb lt detect lt detect r ltb dv o ut 25 a ------------------ = c ltb 1 2 nr ltb f sw ?? ? ------------------------------------------------- - =
layout guidelines L6717 52/56 doc id 17326 rev 1 13 layout guidelines layout is one of the most important things to consider when designing high current applications. a good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops. two kind of critical components and connections have to be considered when laying-out a vrm based on L6717: power components and connections and small signal components connections. 13.1 power components and connections these are the components and connections where switching and high continuous current flows from the input to the load. the first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. to minimize noise and voltage sp ikes (emi and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. the critical components, i.e. the power transistors, must be close one to the other. the use of multi-layer printed circuit board is recommended. traces between the driver section and the mosfets should be wide to minimize the inductance of the trace so minimizing ringing in the driving signals. moreover, vias count needs to be minimized to reduce the related parasitic effect. locate the bypass capacitor (vcc, vccdr and boot capacitors) close to the device with the shortest possible loop and use wide copp er traces to minimize parasitic inductance. systems that do not use schottky diodes in parallel to the low-side mosfet might show big negative spikes on the phase pin. this spike can be limited as well as the positive spike but it causes the bootstrap capacitor to be over-c harged. this extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to- phase voltage overcomes the abs.max.ratings also causing device failures. it is then suggested in this cases to limit this extra-ch arge by adding a small resistor r boot in series to the boot capacitor or the boot diode. the use of r boot also contributes in the limitation of the spike present on the boot pin. figure 20. driver turn-on and turn-off paths r gate r int c gd c g s c d s vccdr l s x driver l s mo s fet gnd (pad) lgatex r gate r int c gd c g s c d s bootx h s x driver h s mo s fet pha s ex hgatex r boot
L6717 layout guidelines doc id 17326 rev 1 53/56 for heat dissipation, place copper area under the ic. this copper area must be connected with internal copper layers through several vias to improve the thermal conductivity. the combination of copper pad, copper plane and vias under the controller allows the device to reach its best thermal performances. 13.2 small signal components and connections these are small signal components and connecti ons to critical nodes of the application as well as bypass capacitors for the device supp ly. locate the bypass capacitor close to the device and refer sensible components such as frequency set-up resistor r osc , offset resistor and ovp resistor r ovp to sgnd (when applicable). star grounding is suggested: use the device exposed pad as a connection point. vsen pin filtered vs. sgnd helps in reducing noise inje ction into device and en pin filtered vs. sgnd helps in reducing false trip due to co upled noise: take care in routing driving net for this pin in order to minimize coupled noise. remote buffer connection must be routed as parallel nets from the fbg/fbr pins to the load in order to avoid the pick-up of any common mode noise. connecting these pins in points far from the load will cause a non-optimum load regulation, in creasing output tolerance. locate current reading components close to the device. the pcb traces connecting the reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up of any common mode noise. it's also important to avoid any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements. symmetrical layout is also suggested. small filtering capacitor can be added, near the controller, between v out and sgnd, on the csxn line when reading across inductor to allow higher layout flexibility.
vfqfpn48 mechanical data and package dimensions L6717 54/56 doc id 17326 rev 1 14 vfqfpn48 mechanical data and package dimensions in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. figure 21. vfqfpn48 mechanical data and package dimensions outline and mechanical data dim. mm min. typ. max. min. typ. max. a 0.800 0.900 1.000 31.50 39.37 a3 0.200 7.874 b 0.180 0.250 0.300 7.087 9.843 11.81 d 6.900 7.000 7.100 271.6 275.6 279.5 d2 5.050 5.150 5.250 198.8 . 202.7 206.7 e 6.900 7.000 7.100 e2 5.050 5.150 5.250 e 0.500 19.68 l 0.300 0.400 0.500 11.81 15.75 ddd 0.080 3.150 vfqfpn-48 (7x7x1.0mm) v ery f ine q uad f lat p ackage n o lead ddd mils 35.43 271.6 275.6 279.5 198.8 202.7 206.7 19.68
L6717 revision history doc id 17326 rev 1 55/56 15 revision history table 21. document revision history date revision changes 29-mar-2010 1 initial release.
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